Along with the development of semiconductor manufacturing technologies, the high integration of transistors has been realized and processors have achieved high computing power. On the other hand, there has been a problem of large power consumption due to high operating frequencies and leakage current of the processors. As a method to avoid this problem, as described in C. Scott Ananian, Krste Asanovic, Bradley C. Kuszmaul, Charles E. Leiserson, and Sean Lie, “Cache Refill/Access Decoupling for Vector Machines”, 37th International Symposium on Microarchitecture (MICRO-37), Portland, Oreg., December 2004 (Non-Patent Document 2), a method in which plural SIMD (Single Instruction Multi Data) processors or plural vector processors are coupled in common to a main memory or a cache memory has been known. According to this method, by arranging many computing units while suppressing the power consumption without increasing the operating frequency, high computing power is realized.
Further, Japanese Patent Application Laid-Open Publication No. 2006-268070 (Patent Document 1) has disclosed a compilation processing method in which object codes for parallel computers are generated by the use of the section parallelization to divide command rows in the loop together with the element parallelization to divide elements of loop control variables. Also, Japanese Patent Application Laid-Open Publication No. 2000-20482 (Patent Document 2) has described a compiling method in which multiple loops having data dependence existing over loop repetitions can be parallelly executed in a pipeline manner by a multiprocessor. In this method, a loop to issue barrier synchronization is generated before and after the multiple loops, and a sentence to issue the barrier synchronization is generated immediately after the divided loops. In Hanz Zima and Barbara Chapman, translated by Yoichi Muraoka, “Super Compilers”, Ohmsha Ltd., 1995 (Non-Patent Document 1) and A. V. Aho, R. Sethi, J. D. Ullman, “Compilers”, Saiensu-sha Co., Ltd., 1990 (Non-Patent Document 3), concrete methods of packaging compilers and the like have been described.